MC68HC908GR4MP datasheet(167/286 Pages) FREESCALE

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Functional Description

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

167

18.4.2.4 Idle Characters

For TXINV = 0, (output not inverted) a transmitted idle character contains all logic 1s and has no start,

stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing

idle character that begins every transmission.

If the TE bit is cleared during a transmission, the PE2/TxD pin becomes idle after completion of the

transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle

character to be sent after the character currently being transmitted.

NOTE

When a break sequence is followed immediately by an idle character, this

SCI design exhibits a condition in which the break character length is

reduced by one half bit time. In this instance, the break sequence will

consist of a valid start bit, eight or nine data bits (as defined by the M bit in

SCC1) of 0 and one half data bit length of 0 in the stop bit position followed

immediately by the idle character. To ensure a break character of the

proper length is transmitted, always queue up a byte of data to be

transmitted while the final break sequence is in progress.

When queueing an idle character, return the TE bit to 1 before the stop bit

of the current character shifts out to the TxD pin. Setting TE after the stop

bit appears on TxD causes data previously written to the SCDR to be lost.

A good time to toggle the TE bit for a queued idle character is when the

SCTE bit becomes set and just before writing the next byte to the SCDR.

18.4.2.5 Inversion of Transmitted Output

The transmit inversion bit (TXINV) in SCI control register 1 (SCC1) reverses the polarity of transmitted

data. All transmitted values, including idle, break, start, and stop bits, are inverted when TXINV is at

logic 1. See 18.8.1 SCI Control Register 1.

18.4.2.6 Transmitter Interrupts

These conditions can generate CPU interrupt requests from the SCI transmitter:

•

SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates that the SCDR has transferred

a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request.

Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate

transmitter CPU interrupt requests.

•

Transmission complete (TC) — The TC bit in SCS1 indicates that the transmit shift register and the

SCDR are empty and that no break or idle character has been generated. The transmission

complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU

interrupt requests.

18.4.3 Receiver

Figure 18-5 shows the structure of the SCI receiver.

MC68HC908GR4MP Datasheet(PDF) 167 Page - Freescale Semiconductor, Inc

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