M68ICS08KX datasheet(34/77 Pages) MOTOROLA

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User’s Manual

M68ICS08KX In-Circuit Simulator

Support Information

MOTOROLA

Support Information

3.4.1.2 VTST Power

VTST is created by a voltage regulator, MC34063, nominally set for 8.6VDC.

This keeps the worst case voltage at greater than VDD +3VDC, meeting VTST

voltage minimums. The voltage may be monitored at VTST test point TP2.

VTST is used during start-up to force the MCU into the Monitor Mode.

3.4.1.3 Reset on Power-up

At initial power-on to the MCU, there is a delay of a few hundred milliseconds

during which the signal ICS_RST# is held low, as set by U8 (DS1233).

When ICS_RST# goes high, the binary ripple counter, U3, begins counting

clock cycles, at the 9.8304MHz rate of the clock Y1. After 1024 clock cycles

are counted, the DELAY_RESET signal toggles and the counter stops counting.

The delayed reset signal is used to turn-on communications to the MCU and to

hold several MCU pins in appropriate states to force Monitor Mode on

power-up.

3.4.2 Serial Communications

Serial communication in half-duplex mode, using PTA0 for transmit and

receive, to the MCU is via the DE9 connector, J6. Pin 2 is the path for transmit

signals and pin 3 is for receive signals. Pin 4, the DTR signal, is utilized as an

input to provide the software host with the ability to turn MCU power on and

off. The RTS signal on contact 7 is used as an input to provide the software host

with the ability to control the IRQ* high voltage.

Serial communication to the MCU does not occur until DELAY_RESET

becomes active high 1024 clock cycles after the RESET signal is high (para

3.4.1.3).

3.4.3 Clock Selection

The source of timing for the MCU may be either the KXICS board’s clock Y1

or the MCU’S internal clock. Selection is by jumper header W-4 (Table 2-1).

M68ICS08KX Datasheet(PDF) 34 Page - Motorola, Inc