RA4L1 datasheet(47/125 Pages) RENESAS

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HOCO clock

HOCOCR.HCSTP

fHOCOWT

Figure 2.8

HOCO clock oscillation start timing (started by setting the HOCOCR.HCSTP bit)

PLLCR.PLLSTP

OSCSF.PLLSF

PLL clock

tPLLWT

PLL circuit output

Figure 2.9

PLL clock oscillation start timing (PLL is Operated after Main Clock Oscillation Has Settled)

Sub-clock oscillator output

SOSCCR.SOSTP

tSUBOSC

Figure 2.10

Sub-clock oscillation start timing

2.3.3

Reset Timing

Table 2.27

Reset timing

Parameter

Symbol

Min

Typ

Max

Unit

Test

conditions

RES pulse width

At power-on

tRESWP

—

Figure 2.11

Not at power-on

tRESW

—

µs

Figure 2.12

Wait time after RES cancellation (at

power-on)

LVD0 enabled*1

tRESWT

—

1.0

—

Figure 2.11

LVD0 disabled*2

—

0.3

—

Wait time after RES cancellation (during

powered-on state)

LVD0 enabled*1

tRESWT2

—

0.9

—

Figure 2.12

LVD0 disabled*2

—

0.2

—

Wait time after internal reset

cancellation (IWDT reset, WDT reset,

RAM parity error reset, RAM ECC error

reset, Bus master MPU error reset,

TrustZone error reset, Cache parity

error reset, Software reset)

LVD0 enabled*1

tRESWT3

—

0.9

—

Figure 2.13

LVD0 disabled*2

—

0.2

—

Note 1. When OFS1.LVDAS = 0.

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

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