RA4L1 datasheet(52/125 Pages) RENESAS

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Note 1. tPcyc indicates the PCLKB cycle.

Note 2. tNMICK indicates the cycle of the NMI digital filter sampling clock.

Note 3. tIRQCK indicates the cycle of the IRQi digital filter sampling clock (i = 0 to 7).

tNMIW

NMI

Figure 2.16

NMI interrupt input timing

tIRQW

IRQ

Figure 2.17

IRQ interrupt input timing

2.3.6

I/O Ports, POEG, GPT, AGT, and ADC12 Trigger Timing

Table 2.34

I/O Ports, POEG, GPT, AGT, and ADC12 trigger timing

Parameter

Symbol

Min

Max

Unit

Test

conditions

I/O Ports

Input data pulse width

2.7 V ≤ VCC ≤ 3.6 V

tPRW

—

tPcyc

Figure 2.18

2.4 V ≤ VCC < 2.7 V

1.6 V ≤ VCC < 2.4 V

POEG

POEG input trigger pulse width

tPOEW

—

tPcyc

Figure 2.19

GPT

Input capture pulse width

Single edge

tGTICW

1.5

—

tPDcyc

Figure 2.20

Dual edge

2.5

—

AGT

AGTIO, AGTEE input cycle

1.8 V ≤ VCC ≤ 3.6 V

tACYC*1

250

—

Figure 2.21

1.6 V ≤ VCC < 1.8 V

2000

—

AGTIO, AGTEE input high-level

width, low-level width

1.8 V ≤ VCC ≤ 3.6 V

tACKWH,

tACKWL

100

—

1.6 V ≤ VCC < 1.8 V

800

—

AGTIO, AGTO, AGTOA,

AGTOB output cycle

2.7 V ≤ VCC ≤ 3.6 V

tACYC2

62.5

—

Figure 2.21

2.4 V ≤ VCC < 2.7 V

125

—

1.8 V ≤ VCC < 2.4 V

250

—

1.6 V ≤ VCC < 1.8 V

500

—

ADC12

12-bit A/D converter trigger input pulse width

tTRGW

1.5

—

tPcyc

Figure 2.22

Note 1. Constraints on AGTIO input: tPcyc × 2 (tPcyc: PCLKB cycle) < tACYC.

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

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