RA4L1 datasheet(67/125 Pages) RENESAS

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Table 2.40

QSPI timing (2 of 2)

Parameter

Symbol

Min

Max

Unit

Test conditions

Data input

setup time

2.4 ≤ VCC ≤ 3.6

tSu

—

Figure 2.39

1.8 ≤ VCC < 2.4

—

1.6 ≤ VCC < 1.8

—

Data input

hold time

1.8 ≤ VCC < 3.6

tIH

—

1.6 ≤ VCC < 1.8

—

QSSL

setup time

2.4 ≤ VCC ≤ 3.6

tSu

(N + 0.5) × tQscyc − 9*1

(N + 0.5) × tQscyc +

100*1

1.8 ≤ VCC < 2.4

(N + 0.5) × tQscyc − 15*1

(N + 0.5) × tQscyc +

100*1

1.6 ≤ VCC < 1.8

(N + 0.5) × tQscyc − 24*1

(N + 0.5) × tQscyc +

100*1

QSSL hold

time

1.8 ≤ VCC ≤ 3.6

tLAG

(N + 0.5) × tQscyc − 5*2

(N + 0.5) × tQscyc +

100*2

1.6 ≤ VCC < 1.8

(N + 0.5) × tQscyc − 8*2

(N + 0.5) × tQscyc +

100*2

Data

output

delay

2.4 ≤ VCC ≤ 3.6

tOD

—

1.8 ≤ VCC < 2.4

—

1.6 ≤ VCC < 1.8

—

Data

output hold

time

1.8 ≤ VCC ≤ 3.6

tOH

−3.3

—

1.6 ≤ VCC < 1.8

−6.3

—

Successive transmission delay

tTD

tQScyc

Note:

tPcyc: PCLKA cycle.

Note 1. N is set to 0 or 1 in SFMSLD.

Note 2. N is set to 0 or 1 in SFMSHD.

tQScyc

QSPCLK output

tQSWH

tQSWL

Figure 2.38

QSPI clock timing

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

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