RA4L1 datasheet(69/125 Pages) RENESAS

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Table 2.41

IIC timing (1) (2 of 2)

Conditions: VCC = AVCC0 = 1.8 to 3.6 V

Parameter

Symbol

Min*1

Max*1

Unit Test conditions

IIC (Fast mode)

ICFER.FMPE = 0

SCL input cycle time

tSCL

6 (12) × tIICcyc + 600

—

Figure 2.40

SCL input high pulse width

tSCLH

3 (6) × tIICcyc + 300

—

SCL input low pulse width

tSCLL

3 (6) × tIICcyc + 300

—

SCL, SDA rise time

tSr

—

300

SCL, SDA fall time

tSf

—

300

SCL, SDA input spike pulse

removal time

tSP

1 (4) × tIICcyc

SDA input bus free time (When

wakeup function is disabled)

tBUF

3 (6) × tIICcyc + 300

—

SDA input bus free time (When

wakeup function is enabled)

tBUF

3 (6) × tIICcyc + 4 ×

tPcyc+ 300

—

START condition input hold time

(When wakeup function is disabled)

tSTAH

tIICcyc + 300

—

START condition input hold time

(When wakeup function is enabled)

tSTAH

1 (5) × tIICcyc + tPcyc +

300

—

Repeated START condition input

setup time

tSTAS

300

—

STOP condition input setup time

tSTOS

300

—

Data input setup time

tSDAS

tIICcyc + 50

—

Data input hold time

tSDAH

—

SCL, SDA capacitive load

Cb*2

—

400

Note:

Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. The AC portion of the

electrical characteristics is measured for each group.

Note:

tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle

Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.

Note 2. Cb indicates the total capacity of the bus line.

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

Page 69 of 125

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