RA4L1 datasheet(63/125 Pages) RENESAS

63 / 125 page

Table 2.39

SPI timing (3 of 3)

Parameter

Symbol

Min

Max

Unit

Test conditions

Slave access time

2.7 V ≤ VCC ≤ 3.6 V

tSA

—

2 × tPcyc + 11

Figure 2.36 and

Figure 2.37

C = 30 pF

2.4 V ≤ VCC < 2.7 V

—

2 × tPcyc + 15

1.8 V ≤ VCC < 2.4 V

—

2 × tPcyc + 35

1.6 V ≤ VCC < 1.8 V

—

2 × tPcyc + 55

Slave output release time

2.7 V ≤ VCC ≤ 3.6 V

tREL

—

2 × tPcyc + 11

2.4 V ≤ VCC < 2.7 V

—

2 × tPcyc + 15

1.8 V ≤ VCC < 2.4 V

—

2 × tPcyc + 35

1.6 V ≤ VCC < 1.8 V

—

2 × tPcyc + 55

Note:

tPcyc: PCLKA cycle.

Note 1. N is set as an integer from 1 to 8 by the SPCKD register.

Note 2. N is set as an integer from 1 to 8 by the SSLND register.

RSPCKn

master select

output

RSPCKn

slave select input

tSPCKWH

VOH

VOL

VOH

tSPCKWL

tSPCKr

tSPCKf

VOL

tSPcyc

tSPCKWH

VIH

VIL

VIH

tSPCKWL

tSPCKr

tSPCKf

VIL

tSPcyc

VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC

Note:

n = A or B

Figure 2.31

SPI clock timing

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

Page 63 of 125

RA4L1 Datasheet(PDF) 63 Page - Renesas Technology Corp

RA4L1 Datasheet(HTML) 63 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL