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RA4L1 Datasheet(PDF) 1 Page - Renesas Technology Corp |
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RA4L1 Datasheet(HTML) 1 Page - Renesas Technology Corp |
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1 / 125 page  RA4L1 Group Renesas Microcontrollers The RA4L1 group features low power, 32-bit microcontrollers (MCUs) based on the Arm® Cortex®-M33 (CM33) core with TrustZone®, delivering an ideal balance of low voltage operation, low power consumption, and high performance. The RA4L1 offers operation down to 1.6V combined with a low power standby current of as little as 1.65µA and a multitude of low power features enabling the user to dynamically optimize power/performance to their application requirements. Features R01DS0447EJ0131 Rev.1.31 May 26, 2026 ■ Arm® Cortex®-M33 Core ● Armv8-M architecture with the main extension ● Maximum operating frequency: 80 MHz ● Arm Memory Protection Unit (Arm MPU) – Protected Memory System Architecture (PMSAv8) – Secure MPU (MPU_S): 8 regions – Non-secure MPU (MPU_NS): 8 regions ● SysTick timer – Embeds two Systick timers: Secure and Non-secure instance – Driven by LOCO or system clock ● CoreSight™ ETM-M33 ■ Memory ● Up to 512-KB code flash memory ● 8-KB data flash memory (100,000 program/erase (P/E) cycles) ● 64-KB SRAM ■ Connectivity ● Serial Communications Interface (SCI) × 6 – Asynchronous interfaces – 8-bit clock synchronous interface – Smart card interface – Simple IIC – Simple SPI – Simple LIN (SCI1) – Manchester coding (SCI3, SCI4) ● IrDA interface (IrDA) ● I2C bus interface (IIC) ● I3C bus interface (I3C) ● Serial Interface UARTA (UARTA) × 2 ● Serial Peripheral Interface (SPI) ● Quad Serial Peripheral Interface (QSPI) ● USB 2.0 Full-Speed Module (USBFS) ● CAN with Flexible Data-rate (CANFD) ● Serial Sound Interface Enhanced (SSIE) ■ Analog ● 12-bit A/D Converter (ADC12) ● 12-bit D/A Converter (DAC12) ● Low-Power Analog Comparator (ACMPLP) × 2 ● Temperature Sensor (TSN) ■ Timers ● General PWM Timer 32-bit (GPT32) × 2 ● General PWM Timer 16-bit (GPT16) × 4 ● Low Power Asynchronous General Purpose Timer (AGT) × 2 ■ Security and Encryption ● Renesas Secure IP (RSIP-E11A) – Symmetric algorithms: AES – Asymmetric algorithms: ECC – Hash-value generation: SHA224, SHA256 – 128-bit unique ID ● Arm® TrustZone® – Up to three or six regions for the code flash, depending on the bank mode – Up to two regions for the data flash – Up to three regions for the SRAM – Individual secure or non-secure security attribution for each peripheral ● Device lifecycle management ● Pin function – Up to three tamper pins – Secure pin multiplexing ■ System and Power Management ● Low power modes ● Realtime Clock (RTC) ● Event Link Controller (ELC) ● Data Transfer Controller (DTC) ● DMA Controller (DMAC) × 8 ● Power-on reset ● Low Voltage Detection (LVD) with voltage settings ● Watchdog Timer (WDT) ● Independent Watchdog Timer (IWDT) ■ Human Machine Interface (HMI) ● Capacitive Touch Sensing Unit (CTSU) ● Segment LCD Controller (SLCDC) ■ Multiple Clock Sources ● Main clock oscillator (MOSC) (1 to 20 MHz) ● Sub-clock oscillator (SOSC) (32.768 kHz) ● High-speed on-chip oscillator (HOCO) (48/64/80 MHz) ● Middle-speed on-chip oscillator (MOCO) (8 MHz) ● Low-speed on-chip oscillator (LOCO) (32.768 kHz) ● IWDT-dedicated on-chip oscillator (15 kHz) ● Clock trim function for HOCO/MOCO/LOCO ● PLL ● Clock out support ■ General-Purpose I/O Ports ● 5-V tolerance, open drain, input pull-up ■ Operating Voltage ● VCC: 1.6 to 3.6 V ■ Operating Temperature and Packages ● Ta = -40 °C to +125 °C – 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch) – 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch) – 48-pin LQFP (7 mm × 7 mm, 0.5 mm pitch) – 48-pin QFN (7 mm × 7 mm, 0.5 mm pitch) – 100-pin BGA (7 mm × 7 mm, 0.5 mm pitch) – 64-pin BGA (5.5 mm × 5.5 mm, 0.65 mm pitch) – 72-pin WLCSP (3.64 mm × 4.28 mm, 0.4 mm pitch) Datasheet R01DS0447EJ0131 Rev.1.31 May 26, 2026 Page 1 of 125 |
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