RA4L1 datasheet(60/125 Pages) RENESAS

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tDr, tDf

tSA

tOH

tLEAD

tTD

tLAG

LSB OUT

(Last data)

DATA

MSB OUT

MSB IN

DATA

LSB IN

MSB IN

LSB OUT

tSU

tOD

tREL

MSB OUT

SSn

input

SCKn

CKPOL = 1

input

SCKn

CKPOL = 0

input

MISOn

output

MOSIn

input

Note:

n = 0, 1, 3 to 5, 9

Figure 2.29

SCI simple SPI mode timing (slave, CKPH = 0)

Table 2.38

SCI timing (3)

Conditions: VCC = AVCC0 = 1.6 to 3.6 V

Parameter

Symbol

Min

Max

Unit

Test conditions

Simple IIC

(Standard mode)

SDA input rise time

tSr

—

1000

Figure 2.30

SDA input fall time

tSf

—

300

SDA input spike pulse removal time

tSP

4 × tIICcyc*1

Data input setup time

tSDAS

250

—

Data input hold time

tSDAH

—

SCL, SDA capacitive load

Cb*2

—

400

Simple IIC (Fast

mode)

SDA input rise time

tSr

—

300

Figure 2.30

SDA input fall time

tSf

—

300

SDA input spike pulse removal time

tSP

4 × tIICcyc*1

Data input setup time

tSDAS

100

—

Data input hold time

tSDAH

—

SCL, SDA capacitive load

Cb*2

—

400

Note 1. tIICcyc: Clock cycle selected by the SMR.CKS[1:0] bits.

Note 2. Cb indicates the total capacity of the bus line.

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

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