RA4L1 datasheet(50/125 Pages) RENESAS

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Table 2.30

Timing of recovery from low power modes (3)

Parameter

Symbol

Min Typ

Max

Unit

Test conditions

Recovery

time from

Software

Standby

mode*1

Low speed

mode

Crystal resonator

connected to main

clock oscillator

System clock source is

main clock oscillator (20

MHz)*2 *4

tSBYMC

—

2.1

2.7

Figure 2.14

External clock input

to main clock

oscillator

System clock source is

main clock oscillator (20

MHz)*3 *4

tSBYEX

—

µs

System clock source is MOCO (8 MHz)*5

tSBYMO

—

µs

Note 1. The division ratio of ICLK, FCLK and PCLKx is the minimum division ratio within the allowable frequency range. The recovery time

is determined by the system clock source.

Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05.

Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00.

Note 4. The ICLK is 0.625 MHz (20/32 MHz)

Note 5. The ICLK is 1 MHz (8 MHz/8)

Table 2.31

Timing of recovery from low power modes (4)

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Recovery time

from Software

Standby mode*1

Subosc-speed mode

System clock source

is sub-clock oscillator

(32.768 kHz)

tSBYSC

—

0.8

0.9

Figure 2.14

System clock source is

LOCO (32.768 kHz)

tSBYLO

—

0.8

Note 1. The sub-clock oscillator or LOCO itself continues oscillating in Software Standby mode during Subosc-speed mode.

Oscillator

ICLK

IRQ

Software Standby mode

tSBYSC, tSBYLO

Oscillator

ICLK

IRQ

Software Standby mode

tSBYMC, tSBYPC, tSBYEX,

tSBYPE, tSBYMO, tSBYHO

Figure 2.14

Software Standby mode cancellation timing

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

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