RA4L1 datasheet(75/125 Pages) RENESAS

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As a product specification, if this Max value cannot be guaranteed, change this Max value and specify that it cannot be used in the

Mixed Bus.

Note 5. On a legacy bus where I2C devices need to see Start

Note 6. Slaves that do not support the optional ENTASx CCCs shall use the tCAS Max value shown for ENTAS3

Note 7. On a mixed bus with Fm Legacy I2C Devices, tAVAL is 300 ns shorter than the Fm Bus Free Condition time (tBUF)

Table 2.47

I3C timing (push-pull timing parameters for SDR mode)

Conditions: VCC = 3.0 to 3.60 V

Parameter

Symbol

Min

Max

Unit

I3C Push-Pull

Timing

Parameters for

SDR and HDR-

DDR Modes

SCL Clock Frequency

fSCL*1

0.01

6.38

MHz

SCL Clock Low Period

tLOW

—

tDIG_L*2 *4

—

SCL Clock High Period for

Mixed Bus

tHIGH_MIXED

—

tDIG_H_MIXED*2 *3

—

SCL Clock High Period

tHIGH

—

tDIG_H*2

—

Clock in to Data Out for Slave

tSCO

—

SCL Clock Rise Time

tCR

—

150 × 1 /fSCL(capped at 60)

SCL Clock Fall Time

tCF

—

150 × 1 /fSCL(capped at 60)

µs

SDA Signal Data

Hold in Push-Pull

Mode

Master

tHD_PP*4

tCR + 3, tCF +3

—

Slave

tHD_PP

—

SDA Signal Data Setup in

Push-Pull Mode

tSU_PP

N/A

Clock After Repeated START

(Sr)

tCASr

tCASmin

N/A

Clock Before Repeated START

(Sr)

tCBSr

tCASmin / 2

N/A

Capacitive Load per Bus Line

(SDA/SCL)

—

Note 1. fSCL = 1 / (tDIG_L + tDIG_H)

Note 2. tDIG_L and tDIG_H are the clock Low and High periods as seen at the receiver end of the I3C Bus using VIL and VIH.

Note 3. When communicating with an I3C Device on a mixed Bus, the tDIG_H_MIXED period must be constrained in order to make sure that

I2C Devices do not interpret I3C signaling as valid I2C signaling.

Note 4. As both edges are used, the hold time needs to be satisfied for the respective edges; i.e., tCF + 3 for falling edge clocks, and tCR + 3

for rising edge clocks.

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

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