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tDr, tDf

tSU

tLEAD

tTD

tLAG

tSA

MSB IN

DATA

LSB IN

MSB IN

MSB OUT

DATA

LSB OUT

MSB IN

MSB OUT

tOH

tOD

tREL

SSLn0

input

RSPCKn

CPOL = 0

input

RSPCKn

CPOL = 1

input

MISOn

output

MOSIn

input

Note:

n = A or B

Figure 2.36

SPI timing (slave, CPHA = 0)

SSLn0

input

RSPCKn

CPOL = 0

input

RSPCKn

CPOL = 1

input

MISOn

output

MOSIn

input

tDr, tDf

tSA

tOH

tLEAD

tTD

tLAG

LSB OUT

(Last data)

DATA

MSB OUT

MSB IN

DATA

LSB IN

MSB IN

LSB OUT

tSU

tOD

tREL

MSB OUT

Note:

n = A or B

Figure 2.37

SPI timing (slave, CPHA = 1)

2.3.10

QSPI Timing

Table 2.40

QSPI timing (1 of 2)

Parameter

Symbol

Min

Max

Unit

Test conditions

QSPCK

clock cycle

2.4 ≤ VCC ≤ 3.6

tQScyc

—

Figure 2.38

1.8 ≤ VCC < 2.4

100

—

1.6 ≤ VCC < 1.8

500

—

QSPCK clock high pulse width

tQSWH

tQScyc × 0.4

—

QSPCK clock low pulse width

tQSWL

tQScyc × 0.4

—

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

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