RA4L1 datasheet(13/125 Pages) RENESAS

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Table 1.16

Pin functions (2 of 4)

Function

Signal

I/O

Description

SCI

SCKn

I/O

Input/output pins for the clock (clock synchronous mode)

RXDn

Input

Input pins for received data (asynchronous mode/clock synchronous

mode)

TXDn

Output

Output pins for transmitted data (asynchronous mode/clock

synchronous mode)

CTSn_RTSn

I/O

Input/output pins for controlling the start of transmission and

reception (asynchronous mode/clock synchronous mode), active-

low.

CTSn

Input

Input for the start of transmission.

SCLn

I/O

Input/output pins for the IIC clock (simple IIC mode)

SDAn

I/O

Input/output pins for the IIC data (simple IIC mode)

SCKn

I/O

Input/output pins for the clock (simple SPI mode)

MISOn

I/O

Input/output pins for slave transmission of data (simple SPI mode)

MOSIn

I/O

Input/output pins for master transmission of data (simple SPI mode)

RXDXn

Input

Input pins for received data (Simple LIN Mode)

TXDXn

Output

Output pins for transmitted data (Simple LIN Mode)

SIOXn

I/O

Input/output pins for received or transmitted data (Simple LIN Mode)

SSn

Input

Chip-select input pins (simple SPI mode), active-low

IIC

SCLn

I/O

Input/output pins for the clock

SDAn

I/O

Input/output pins for data

I3C

I3C_SCL0

I/O

Input/output pin for clock

I3C_SDA0

I/O

Input/output pin for data

UARTA

RxDAn

Input

Serial data input signal

TxDAn

Output

Serial data output signal

CLKAn

Output

Serial clock output signal

SPI

RSPCKA

I/O

Clock input/output pin

MOSIA

I/O

Input or output pin for data output from the master

MISOA

I/O

Input or output pin for data output from the slave

SSLA0

I/O

Input or output pin for slave selection

SSLA1 to SSLA3

Output

Output pins for slave selection

CANFD

CRXn

Input

Receive data

CTXn

Output

Transmit data

RA4L1 Datasheet

1. Overview

R01DS0447EJ0131 Rev.1.31

May 26, 2026

Page 13 of 125

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