DA7282-00FVC datasheet(5/75 Pages) RENESAS

5 / 75 page

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory

R15DS0041EE0330 Rev.3.30

June 16, 2026

CFR0011-120-00

Page 5

Figure 3: DA7282 pinout diagrams (top view) for WLCSP (left) and QFN (right).................................................. 10

Figure 4. I2C interface timing ................................................................................................................................. 13

Figure 5. LRA output acceleration swept in frequency with constant power input signal...................................... 15

Figure 6. Narrowband and wideband LRA response across frequency................................................................ 16

Figure 7. Dual mode LRA response across frequency.......................................................................................... 16

Figure 8. System state diagram............................................................................................................................. 19

Figure 9. Example PWM inputs with ACCELERATION_EN = 0 ........................................................................... 21

Figure 10. LRA single step drive without acceleration and rapid stop .................................................................. 23

Figure 11. LRA single step with acceleration and rapid stop ................................................................................ 23

Figure 12. Simple drive (top) versus active acceleration and rapid stop enabled (bottom) .................................. 24

Figure 13. Operation in DRO mode....................................................................................................................... 27

Figure 14. Operation in PWM mode ...................................................................................................................... 28

Figure 15. Operation in RTWM mode.................................................................................................................... 29

Figure 16. Operation in ETWM mode.................................................................................................................... 31

Figure 17. Output voltage and current for different AMP_PID_EN values ............................................................ 34

Figure 18. Custom wave point numbering............................................................................................................. 35

Figure 19. Half-period control in DRO mode ......................................................................................................... 36

Figure 20. Polarity timing relationship ................................................................................................................... 36

Figure 21. Equivalent electrical model of an actuator ........................................................................................... 37

Figure 22. Automatic output limiting ...................................................................................................................... 38

Figure 23. Coin ERM physical and electrical summary......................................................................................... 39

Figure 24. VDDIO pin control in push-pull configuration and open drain configuration ........................................ 40

Figure 25. Waveform memory structure ................................................................................................................ 41

Figure 26: Snippet ramp and step with ACCELERATION_EN = 1 ....................................................................... 43

Figure 27. Snippet example................................................................................................................................... 43

Figure 28. Command structure for a single frame ................................................................................................. 44

Figure 29. Sequence structure .............................................................................................................................. 45

Figure 30. Waveform memory example ................................................................................................................ 46

Figure 31. Overview of data formats with acceleration disabled ........................................................................... 47

Figure 32. Overview of data formats with acceleration enabled............................................................................ 48

Figure 33. Schematic of the I2C control interface bus ........................................................................................... 50

Figure 34. I2C START and STOP conditions......................................................................................................... 50

Figure 35. I2C byte write (SDA line)....................................................................................................................... 51

Figure 36. Examples of the I2C byte read (SDA line) ............................................................................................ 51

Figure 37. Examples of I2C page read (SDA line) ................................................................................................. 51

Figure 38. I2C page write (SDA line)...................................................................................................................... 51

Figure 39. I2C repeated write (SDA line) ............................................................................................................... 52

Figure 40. WLCSP package outline drawing......................................................................................................... 68

Figure 41. QFN package outline drawing .............................................................................................................. 69

Figure 42. External components diagram.............................................................................................................. 71

Figure 43. WLCSP example PCB layout ............................................................................................................... 72

Figure 44. QFN example PCB layout .................................................................................................................... 72

Tables

Table 1. DA728x feature comparison ...................................................................................................................... 8

Table 2. Pin description ......................................................................................................................................... 10

Table 3. Pin type definition .................................................................................................................................... 10

Table 4. Absolute maximum ratings ...................................................................................................................... 11

DA7282-00FVC Datasheet(PDF) 5 Page - Renesas Technology Corp

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