ADIS16505-2SLASHPCBZ datasheet(27/41 Pages) AD

27 / 41 page

Data Sheet

ADIS16505

Rev. C | Page 27 of 41

Z-Axis Accelerometer (Z_ACCL_LOW and Z_ACCL_OUT)

Table 37. Z_ACCL_LOW Register Definition

Addresses

Default

Access

Flash Backup

0x18, 0x19

Not applicable

Table 38. Z_ACCL_LOW Bit Definitions

Bits

Description

[15:0]

Z-axis accelerometer data; additional resolution bits

Table 39. Z_ACCL_OUT Register Definition

Addresses

Default

Access

Flash Backup

0x1A, 0x1B

Not applicable

Table 40. Z_ACCL_OUT Bit Definitions

Bits

Description

[15:0]

Z-axis accelerometer data, high word; twos complement,

±78.3 m/sec2 range; 0 m/sec2 = 0x0000,

1 LSB = 2.45 mm/sec2

The Z_ACCL_LOW (see Table 37 and Table 38) and Z_ACCL_

OUT (see Table 39 and Table 40) registers contain the

accelerometer data for the z-axis.

Internal Temperature (TEMP_OUT)

Table 41. TEMP_OUT Register Definition

Addresses

Default

Access

Flash Backup

0x1C, 0x1D

Not applicable

Table 42. TEMP_OUT Bit Definitions

Bits

Description

[15:0]

Temperature data; twos complement, 1 LSB = 0.1°C,

0°C = 0x0000

The TEMP_OUT register (see Table 41 and Table 42) provides

a coarse measurement of the temperature inside of the ADIS16505.

This data is most useful for monitoring relative changes in the

thermal environment.

Table 43. TEMP_OUT Data Format Examples

Temperature (°C)

Decimal

Hex

Binary

+105

+1050

0x041A

0000 0100 0001 1010

+25

+250

0x00FA

0000 0000 1111 1010

+0.2

0x0002

0000 0000 0000 0010

+0.1

0x0001

0000 0000 0000 0001

0x0000

0000 0000 0000 0000

+0.1

−1

0xFFFF

1111 1111 1111 1111

+0.2

−2

0xFFFE

1111 1111 1111 1110

−40

−400

0xFE70

1111 1110 0111 0000

Time Stamp (TIME_STAMP)

Table 44. TIME_STAMP Register Definition

Addresses

Default

Access

Flash Backup

0x1E, 0x1F

Not applicable

Table 45. TIME_STAMP Bit Definitions

Bits

Description

[15:0]

Time from the last pulse on the SYNC pin; offset binary

format, 1 LSB = 49.02 μs

The TIME_STAMP register (see Table 44 and Table 45) works

in conjunction with scaled sync mode (Register MSC_CTRL,

Bits[3:2] = 10, see Table 106). The 16-bit number in TIME_

STAMP contains the time associated with the last sample in

each data update relative to the most recent edge of the clock

signal in the SYNC pin. For example, when the value in the

UP_SCALE register (see Table 108) represents a scale factor of

20, DEC_RATE = 0, and the external SYNC rate = 100 Hz, the

following time stamp sequence results: 0 LSB, 10 LSB, 20 LSB,

30 LSB, 40 LSB, 50 LSB, 61 LSB, 71 LSB, … , 193 LSB for the 20th

sample, which translates to 0 μs, 490 μs, … , 9460 μs, the time

from the first SYNC edge.

Data Update Counter (DATA_CNTR)

Table 46. DATA_CNTR Register Definition

Addresses

Default

Access

Flash Backup

0x22, 0x23

Not applicable

Table 47. DATA_CNTR Bit Definitions

Bits

Description

[15:0]

Data update counter, offset binary format

When the ADIS16505 goes through its power-on sequence or

when it recovers from a reset command, DATA_CNTR (see

Table 46 and Table 47) starts with a value of 0x0000 and

increments every time new data loads into the output registers.

When the DATA_CNTR value reaches 0xFFFF, the next data

update causes it to wrap back around to 0x0000 where it

continues to increment every time new data loads into the

output registers.

ADIS16505-2/PCBZ Datasheet(PDF) 27 Page - Analog Devices

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