ADIS16505-2SLASHPCBZ datasheet(34/41 Pages) AD

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ADIS16505

Data Sheet

Rev. C | Page 34 of 41

Bits

Description

11 = output sync mode. Identical to internal sync mode,

except the SYNC pin functions as an output signal,

indicating when the internal clock samples sensors.

SYNC polarity (input or output). Changes to this bit

may take up to 200 μs after writing to indicate the new

value during readback.

1 = rising edge triggers sampling.

0 = falling edge triggers sampling (default).

DR polarity. This bit controls the polarity of the DR pin.

Changes to this bit may take up to 200 μs after writing

to indicate the new value during readback.

1 = active high when data is valid.

0 = active low when data is valid (default).

Point of Percussion

for the point of percussion alignment function, which maps the

accelerometer sensors to the corner of the package that is closest

to Pin A1 (see Figure 59). The factory default setting in the

MSC_CTRL register activates this function. To turn this function

off while retaining the rest of the factory default settings in the

MSC_CTRL register, set Register MSC_CTRL, Bit 6 = 0 using

the following command sequence on the DIN pin: 0xE081, then

0xE100.

A10

POINT OF

PERCUSSION

Figure 59. Point of Percussion Reference Point

Linear Acceleration Effect on Gyroscope Bias

control for the linear acceleration compensation in the signal

calibration routines of the gyroscope. The factory default

contents in the MSC_CTRL register enable this compensation.

To turn the compensation off, set Register MSC_CTRL,

Bit 7 = 0 using the following sequence on the DIN pin: 0xE041,

0xEF00.

Sync Mode Select

Refer to the Clock Control section for the functions of the sync

mode select bits.

Sync Input Frequency Multiplier (UP_SCALE)

Table 107. UP_SCALE Register Definition

Addresses

Default

Access

Flash Backup

0x62, 0x63

0x07D0

R/W

Yes

Table 108. UP_SCALE Bit Definitions

Bits

Description

[15:0]

KECSF; binary format. The user must wait until the DR

pin starts toggling after changing this register and/or

MSC_CTRL[3:2] to correctly read back the new values.

However, the user can write these registers in succession

before waiting for the DR pin to resume toggling.

Refer to the Clock Control section for the function and

programming of the UP_SCALE register.

Decimation Filter (DEC_RATE)

Table 109. DEC_RATE Register Definition

Addresses

Default

Access

Flash Backup

0x64, 0x65

0x0000

R/W

Yes

Table 110. DEC_RATE Bit Definitions

Bits

Description

[15:11]

Don’t care

[10:0]

Decimation rate, binary format, maximum = 1999.

Changes to this register may take up to 30 μs after

writing to indicate the new value during readback.

The DEC_RATE register (see Table 109 and Table 110) provides

user control for the averaging decimating filter, which averages

and decimates the gyroscope and accelerometer data; it also

extends the time that the delta angle and the delta velocity track

between each update. When the ADIS16505 operates in internal

clock mode (see Register MSC_CTRL, Bits[3:2], in Table 106),

the nominal output data rate is equal to 2000/(DEC_RATE + 1).

For example, set DEC_RATE = 0x0013 to reduce the output

sample rate to 100 SPS (2000 ÷ 20) using the following DIN pin

sequence: 0xE413, then 0xE500.

Data Update Rate in External Sync Modes

When using the input sync option in scaled sync mode

(Register MSC_CTRL, Bits[3:2] = 10, see Table 106), the

output data rate is equal to

(fSYNC × KECSF)/(DEC_RATE + 1)

where:

fSYNC is the frequency of the clock signal on the SYNC pin.

KESCF is the value from the UP_SCALE register (see Table 108).

When using direct sync mode, KESCF = 1.

ADIS16505-2/PCBZ Datasheet(PDF) 34 Page - Analog Devices

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