S9S08QD2CSC datasheet(53/198 Pages) FREESCALE

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Chapter 5 Resets, Interrupts, and General System Control

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

5.5

Interrupts

Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine

(ISR), and then restore the CPU status so processing resumes where it was before the interrupt. Other than

the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events

such as an edge on the IRQ pin or a timer-overflow event. The debug module can also generate an SWI

under certain circumstances.

If an event occurs in an enabled interrupt source, an associated read-only status flag will become set. The

CPU will not respond until and unless the local interrupt enable is a 1 to enable the interrupt. The I bit in

the CCR is 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset

which masks (prevents) all maskable interrupt sources. The user program initializes the stack pointer and

performs other system setup before clearing the I bit to allow the CPU to respond to interrupts.

When the CPU receives a qualified interrupt request, it completes the current instruction before responding

to the interrupt. The interrupt sequence obeys the same cycle-by-cycle sequence as the SWI instruction

and consists of:

•

Saving the CPU registers on the stack

•

Setting the I bit in the CCR to mask further interrupts

•

Fetching the interrupt vector for the highest-priority interrupt that is currently pending

•

Filling the instruction queue with the first three bytes of program information starting from the

address fetched from the interrupt vector locations

While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of

another interrupt interrupting the ISR itself (this is called nesting of interrupts). Normally, the I bit is

restored to 0 when the CCR is restored from the value stacked on entry to the ISR. In rare cases, the I bit

can be cleared inside an ISR (after clearing the status flag that generated the interrupt) so that other

interrupts can be serviced without waiting for the first service routine to finish. This practice is not

recommended for anyone other than the most experienced programmers because it can lead to subtle

program errors that are difficult to debug.

The interrupt service routine ends with a return-from-interrupt (RTI) instruction which restores the CCR,

A, X, and PC registers to their pre-interrupt values by reading the previously saved information off the

stack.

NOTE

For compatibility with M68HC08 devices, the H register is not

automatically saved and restored. It is good programming practice to push

H onto the stack at the start of the interrupt service routine (ISR) and restore

it immediately before the RTI that is used to return from the ISR.

When two or more interrupts are pending when the I bit is cleared, the highest priority source is serviced

first (see Table 5-2).

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