S9S08QD2CSC datasheet(18/198 Pages) FREESCALE

18 / 198 page

Chapter 1 Device Overview

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

1.3

System Clock Distribution

Figure 1-2 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock

inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module

function. All memory mapped registers associated with the modules are clocked with BUSCLK.

Figure 1-2. System Clock Distribution Diagram

Table 1-2. Versions of On-Chip Modules

Module

Version

Analog-to-Digital Converter

(ADC)

Central Processing Unit

(CPU)

Internal Clock Source

(ICS)

Keyboard Interrupt

(KBI)

Timer Pulse-Width Modulator

(TPM)

TPM1

TPM2

CPU

BDC

ADC2

FLASH3

ICS

ICSOUT

÷2

SYSTEM CONTROL LOGIC

BUSCLK

ICSLCLK1

RTI

1 ICSLCLK is the alternate BDC clock source for the MC9S08QD4 series.

2 ADC has min. and max frequency requirements. See ADC chapter and Appendix A, “Electrical Characteristics.”

3 Flash has frequency requirements for program and erase operation.See Appendix A, “Electrical Characteristics.”

÷2

ICSFFCLK

COP

TCLK1

TCLK2

ICSIRCLK

FIXED FREQ CLOCK (XCLK)

S9S08QD2CSC Datasheet(PDF) 18 Page - Freescale Semiconductor, Inc

S9S08QD2CSC Datasheet(HTML) 18 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL