S9S08QD2CSC datasheet(78/198 Pages) FREESCALE

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Chapter 7 Central Processor Unit (S08CPUV2)

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

7.3.5

Extended Addressing Mode (EXT)

In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of

program memory after the opcode (high byte first).

7.3.6

Indexed Addressing Mode

Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair

and two that use the stack pointer as the base reference.

7.3.6.1

Indexed, No Offset (IX)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of

the operand needed to complete the instruction.

7.3.6.2

Indexed, No Offset with Post Increment (IX+)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of

the operand needed to complete the instruction. The index register pair is then incremented

(H:X = H:X + 0x0001) after the operand has been fetched. This addressing mode is only used for MOV

and CBEQ instructions.

7.3.6.3

Indexed, 8-Bit Offset (IX1)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned

8-bit offset included in the instruction as the address of the operand needed to complete the instruction.

7.3.6.4

Indexed, 8-Bit Offset with Post Increment (IX1+)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned

8-bit offset included in the instruction as the address of the operand needed to complete the instruction.

The index register pair is then incremented (H:X = H:X + 0x0001) after the operand has been fetched. This

addressing mode is used only for the CBEQ instruction.

7.3.6.5

Indexed, 16-Bit Offset (IX2)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus a 16-bit offset

included in the instruction as the address of the operand needed to complete the instruction.

7.3.6.6

SP-Relative, 8-Bit Offset (SP1)

This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit

offset included in the instruction as the address of the operand needed to complete the instruction.

S9S08QD2CSC Datasheet(PDF) 78 Page - Freescale Semiconductor, Inc