S9S08QD2CSC datasheet(60/198 Pages) FREESCALE

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Chapter 5 Resets, Interrupts, and General System Control

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

5.8.3

System Background Debug Force Reset Register (SBDFR)

This high-page register contains a single write-only control bit. A serial background command such as

WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are

ignored. Reads always return 0x00.

COP

Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.

This reset source can be blocked by COPE = 0.

0 Reset not caused by COP timeout.

1 Reset caused by COP timeout.

ILOP

Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP

instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is

considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.

0 Reset not caused by an illegal opcode.

1 Reset caused by an illegal opcode.

ILAD

Illegal Address — Reset was caused by an attempt to access either data or an instruction at an unimplemented

memory address.

0 Reset not caused by an illegal address

1 Reset caused by an illegal address

LVD

Low Voltage Detect — If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset will

occur. This bit is also set by POR.

0 Reset not caused by LVD trip or POR.

1 Reset caused by LVD trip or POR.

321

000

BDFR1

Reset:

000

= Unimplemented or Reserved

1 BDFR is writable only through serial background debug commands, not from user programs.

Figure 5-4. System Background Debug Force Reset Register (SBDFR)

Table 5-5. SBDFR Register Field Descriptions

Field

Description

BDFR

Background Debug Force Reset — A serial background command such as WRITE_BYTE can be used to allow

an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot

be written from a user program. To enter user mode, PTA4/TPM2CH0O/BKGD/MS must be high immediately

after issuing WRITE_BYTE command. To enter BDM, PTA4/TPM2CH0O/BKGD/MS must be low immediately

after issuing WRITE_BYTE command. See A.8.1, “Control Timing,” for more information.

Table 5-4. SRS Register Field Descriptions (continued)

Field

Description

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