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L99DZ70XP Datasheet(PDF) 20 Page - STMicroelectronics |
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L99DZ70XP Datasheet(HTML) 20 Page - STMicroelectronics |
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20 / 47 page ![]() Electrical specifications L99DZ70XP 20/47 Doc ID 15162 Rev 3 16.8 tr in Rise time of input signal DI, CLK, CSN VCC = 5V 100 ns 16.9 tf in Fall time of input signal DI, CLK, CSN VCC = 5V 100 ns 1. DI timing parameters tested in production by a passed / failed test: Tj= -40°C / +25°C: SPI communication @ 2MHz. Tj= +125°C SPI communication @ 1.25 MHz. Table 17. DO Item Symbol Parameter Test condition Min. Typ. Max. Unit 17.1 VDOL Output low level IDO = -5 mA 0.2VCC V 17.2 VDOH Output high level IDO = 5 mA 0.8 VCC V 17.3 IDOLK Tristate leakage current VCSN = VCC, 0V < VDO < VCC -10 10 µA 17.4 CDO (1) 1. Value of input capacity is not measured in production test. Parameter guaranteed by design. Tristate input capacitance VCSN = VCC, 0V < VCC < 5.3V 10 pF Table 18. DO timing Item Symbol Parameter Test condition Min. Typ. Max. Unit 18.1 tr DO DO rise time CDO = 100 pF 80 140 ns 18.2 tf DO DO fall time CDO = 100 pF 50 100 ns 18.3 ten DO tri L DO enable time from tristate to low level CDO = 100 pF, Iload = 1mA pull-up load to VCC 100 250 ns 18.4 tdis DO L tri DO disable time from low level to tristate CDO = 100 pF, Iload = 4 mA pull-up load to VCC 380 450 ns 18.5 ten DO tri H DO enable time from tristate to high level CDO =100 pF, Iload = -1mA pull-down load to GND 100 250 ns 18.6 tdis DO H tri DO disable time from high level to tristate CDO = 100 pF, Iload = -4mA pull-down load to GND 380 450 ns 18.7 td DO DO delay time VDO < 0.3 VCC, VDO > 0.7 VCC, CDO = 100 pF 50 250 ns Table 16. SDI timing (continued)(1) Item Symbol Parameter Test condition Min. Typ. Max. Unit |
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