L99DZ70XP datasheet(37/47 Pages) STMICROELECTRONICS

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L99DZ70XP

SPI - control and status registers

Doc ID 15162 Rev 3

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5.4

Control register 3

Table 28.

Control register 3 (read/write)

Bit

Name

Comment

OUT7-OCR enable

In case of an over-current event the over-current status bit (Status

Recovery Enable bit (OCR) is set the output will be automatically

reactivated after a delay time resulting in a PWM modulated current

with a programmable duty cycle (bit 5). Depending on the

occurrence of the over-current event and the internal clock phase it

is possible that one recovery cycle is executed even if this bit is set

to zero.

OUT8-OCR enable

OUT9-OCR enable

OUT10-OCR enable

OUT11-OCR enable

OUT7 PWM1 enable

If the PWM1/2 Enable bit is set and the output is enabled (control

switched off if PWM1/2 input is low. OUT5, 8 and OUT10 are

controlled by PWM2 input all other outputs are controlled by PWM1

input.

OUT8 PWM2 enable

OUT9 PWM1 enable

OUT10 PWM2 enable

OUT11 PWM1 enable

OCR frequency

0: 1.7 kHz

1: 3 kHz

This bit defines in combination with the over-current recovery bit

(Input Register 1) the over-current recovery frequency of an

activated driver.

OV/UVR disable

If this bit is set the microcontroller has to clear the status register

after undervoltage/overvoltage event to enable the outputs.

CM select bit 3

Depending on combination of bit 3 to 0 the current image of

the selected highside output OUTn will be multiplexed to the

CM/PWM2 output (see table below).

Other combinations deactivate the current monitor.

Bit 3

Bit 2

Bit 1

Bit 0

Current image of

OUT1

CM select bit 2

OUT2

OUT3

OUT4

OUT5

CM select bit 1

OUT6

OUT7

OUT8

OUT9

CM select bit 0

OUT10

OUT11

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