L99DZ70XP datasheet(26/47 Pages) STMICROELECTRONICS

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Application information

L99DZ70XP

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Doc ID 15162 Rev 3

3.9

Open load detection

The open load detection monitors the load current in each activated output stage. If the load

current is below the open load detection threshold for at least 1 ms (tdOL) the corresponding

open load bit is set in the status register. Due to mechanical/electrical inertia of typical loads

a short activation of the outputs (e.g. 3 ms) can be used to test the open load status without

changing the mechanical/electrical state of the loads.

3.10

Over-load detection

In case of an over-current condition a flag is set in the status register in the same way as

during open load detection. If the over-current signal is valid for at least tISC(typ) = 55 µs, the

over-current flag is set and the corresponding driver is switched off to reduce the power

dissipation and to protect the integrated circuit. If the over-current recovery bit of the output

is zero, the microcontroller has to clear the status bits to reactivate the corresponding driver.

3.11

Current monitor

The current monitor output sources a current image at the current monitor output which has

two fixed ratios of the instantaneous current of the selected highside driver. Outputs with a

resistance of 500 m

Ω and higher have a ratio of 1/2000 and those with a lower resistance of

1/10000. The signal at output CM is blanked after switching on the driver until correct

settlement of the circuitry (at least for 64 µs). The bits 0 to 3 of the control register 3 define

which of the outputs are multiplexed to the current monitor output CM/PWM2. The current

monitor output allows a more precise analysis of the actual state of the load rather than the

detection of an open- or overload condition. For example it can be used to detect the motor

state (starting, free-running, stalled). Moreover, it is possible to control the power of the

defroster more precisely by measuring the load current. The current monitor output is

bidirectional (PWM inputs).

3.12

PWM inputs

Each driver has a corresponding PWM enable bit, which can be programmed by the SPI

interface. If the PWM enable bit is set in control registers 2 or 3, the output is controlled by

the logically AND-combination of the PWM signal and the output control bit in Control

Registers 0 and 1. The outputs OUT1-4, 6, 7, 9, OUT11 are controlled by the PWM1 input

and the outputs OUT5, 8 and OUT10 are controlled by the bidirectional input CM/PMW2.

For example, the two PWM inputs can be used to dim two lamps independently by external

PWM signals. In case of switching off a high/low side switch in PWM mode a minimum off

time of appr. (256 µs – tdon+ tdoff) is predefined by the state machine, to avoid switching on

the high/low side again during the negative slope. For a PWM frequency of 100Hz this

means the maximum duty cycle is about 98%. Larger duty cycles can be realized by

applying pulse skipping.

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