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W25Q32FV

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8.2.11 Fast Read Quad I/O (EBh)

The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except

that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy

clocks are required in SPI mode prior to the data output. The Quad I/O dramatically reduces instruction

overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad

Enable bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction.

Fast Read Quad I/O with “Continuous Read Mode”

The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the

“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 24a. The

upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the

inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care

(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.

If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS

is raised and then lowered) does not require the EBh instruction code, as shown in Figure 24b. This

reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered

after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next

instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to

normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4

= 1 and return the device to normal operation.

Figure 24a. Fast Read Quad I/O Instruction (Initial instruction or previous M5-4

≠10, SPI Mode)

M7-0

/CS

CLK

Mode 0

Mode 3

A23-16

A15-8

A7-0

Byte 1

Byte 2

IOs switch from

Input to Output

Byte 3

Dummy

Instruction (EBh)

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