W25Q32FVZPIP datasheet(53/99 Pages) WINBOND

53 / 99 page

W25Q32FV

Publication Release Date: Sept 16,, 2013

- 52 -

Revision H

8.2.17

Sector Erase (20h)

The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all

1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase

Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low

and shifting the instruction code “20h” followed a 24-bit sector address (A23-A0). The Sector Erase

instruction sequence is shown in Figure 31a & 31b.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done

the Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector Erase

instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector Erase

cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of

the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is

finished and the device is ready to accept other instructions again. After the Sector Erase cycle has

finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase

instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB,

BP2, BP1, and BP0) bits or the Individual Block/Sector Locks.

/CS

CLK

(IO

Mode 0

Mode 3

Instruction (20h)

High Impedance

24-Bit Address

Mode 0

Mode 3

= MSB

Figure 31a. Sector Erase Instruction (SPI Mode)

/CS

CLK

Mode 0

Mode 3

20h

Instruction

A23-16

A15-8

A7-0

Mode 0

Mode 3

Figure 31b. Sector Erase Instruction (QPI Mode)

W25Q32FVZPIP Datasheet(PDF) 53 Page - Winbond

W25Q32FVZPIP Datasheet(HTML) 53 Page - Winbond

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

Datasheet Download

Link URL