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W25Q32FVZPIP Datasheet(PDF) 15 Page - Winbond

Part # W25Q32FVZPIP
Description  3V 32M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI
PDF  99 Pages
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Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W25Q32FVZPIP Datasheet(HTML) 15 Page - Winbond

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W25Q32FV
Publication Release Date: Sept 16,, 2013
- 14 -
Revision H
6.1.6
Software Reset & Hardware /RESET pin
The W25Q32FV can be reset to the initial power-on state by a software Reset sequence, either in SPI
mode or QPI mode. This sequence must include two consecutive commands: Enable Reset (66h) &
Reset (99h). If the command sequence is successfully accepted, the device will take approximately 30uS
(tRST) to reset. No command will be accepted during the reset period.
For the WSON-8 and TFBGA package types, W25Q32FV can also be configured to utilize a hardware
/RESET pin. The HOLD/RST bit in the Status Register-3 is the configuration bit for /HOLD pin function or
RESET pin function. When HOLD/RST=0 (factory default), the pin acts as a /HOLD pin as described
above; when HOLD/RST=1, the pin acts as a /RESET pin. Drive the /RESET pin low for a minimum period
of ~1us (tRESET*) will reset the device to its initial power-on state. Any on-going Program/Erase operation
will be interrupted and data corruption may happen. While /RESET is low, the device will not accept any
command input.
If QE bit is set to 1, the /HOLD or /RESET function will be disabled, the pin will become one of the four
data I/O pins.
For the SOIC-16 package, W25Q32FV provides a dedicated /RESET pin in addition to the /HOLD (IO3)
pin as illustrated in Figure 1b. Drive the /RESET pin low for a minimum period of ~1us (tRESET*) will
reset the device to its initial power-on state. The HOLD/RST bit or QE bit in the Status Register will not
affect the function of this dedicated /RESET pin.
Hardware /RESET pin has the highest priority among all the input signals. Drive /RESET low for a
minimum period of ~1us (tRESET*) will interrupt any on-going external/internal operations, regardless the
status of other SPI signals (/CS, CLK, IOs, /WP and/or /HOLD).
Note:
1.While a faster /RESET pulse (as short as a few hundred nanoseconds) will often reset the device, a 1us minimum is
recommended to ensure reliable operation.
2.There is an internal pull-up resistor for the dedicated /RESET pin on the SOIC-16 package. If the reset function is not needed, this
pin can be left floating in the system.



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