W25Q32FVZPIP datasheet(68/99 Pages) WINBOND

68 / 99 page

W25Q32FV

- 67 -

8.2.30 Read SFDP Register (5Ah)

The W25Q32FV features a 256-Byte Serial Flash Discoverable Parameter (SFDP) register that contains

information about device configurations, available instructions and other features. The SFDP parameters

are stored in one or more Parameter Identification (PID) tables. Currently only one PID table is specified,

but more may be added in the future. The Read SFDP Register instruction is compatible with the SFDP

standard initially established in 2010 for PC and other applications, as well as the JEDEC standard

JESD216 that is published in 2011. Most Winbond SpiFlash Memories shipped after June 2011 (date

code 1124 and beyond) support the SFDP feature as specified in the applicable datasheet.

The Read SFDP instruction is initiated by driving the /CS pin low and shifting the instruction code “5Ah”

followed by a 24-bit address (A23-A0)

(1) into the DI pin. Eight “dummy” clocks are also required before the

SFDP register contents are shifted out on the falling edge of the 40

th CLK with most significant bit (MSB)

first as shown in Figure 34. For SFDP register values and descriptions, please refer to the Winbond

Application Note for SFDP Definition Table.

Note 1: A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256-Byte SFDP Register.

/CS

CLK

(IO

Mode 0

Mode 3

Instruction (5Ah)

High Impedance

24-Bit Address

Data Out 1

/CS

CLK

(IO

Dummy Byte

High Impedance

Data Out 2

= MSB

Figure 34. Read SFDP Register Instruction Sequence Diagram

W25Q32FVZPIP Datasheet(PDF) 68 Page - Winbond