W25Q32FVZPIP datasheet(18/99 Pages) WINBOND

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W25Q32FV

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7.1.4

Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable

The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the

Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table.

The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction

depending on the state of the SRP0, SRP1 and WEL bits.

7.1.5 Sector/Block Protect Bit (SEC) – Volatile/Non-Volatile Writable

The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect

either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the

array as shown in the Status Register Memory Protection table. The default setting is SEC=0.

7.1.6

Complement Protect (CMP) – Volatile/Non-Volatile Writable

The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in

conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once

CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For

instance, when CMP=0, a top 64KB block can be protected while the rest of the array is not; when

CMP=1, the top 64KB block will become unprotected while the rest of the array become read-only. Please

refer to the Status Register Memory Protection table for details. The default setting is CMP=0.

7.1.7

Status Register Protect (SRP1, SRP0) – Volatile/Non-Volatile Writable

The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register

(S8 and S7). The SRP bits control the method of write protection: software protection, hardware

protection, power supply lock-down or one time programmable (OTP) protection.

SRP1

SRP0

/WP

Status

Description

Software

Protection

/WP pin has no control. The Status register can be written to

after a Write Enable instruction, WEL=1. [Factory Default]

Hardware

Protected

When /WP pin is low the Status Register locked and cannot

be written to.

Hardware

Unprotected

When /WP pin is high the Status register is unlocked and can

be written to after a Write Enable instruction, WEL=1.

Power Supply

Lock-Down

Status Register is protected and cannot be written to again

until the next power-down, power-up cycle.

(1)

One Time

Program

(2)

Status Register is permanently protected and cannot be

written to.

Notes:

1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.

2. This feature is available upon special order. Please contact Winbond for details.

W25Q32FVZPIP Datasheet(PDF) 18 Page - Winbond

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