ATXMEGA8E5_14 datasheet(9/147 Pages) ATMEL

9 / 147 page

XMEGA E5 [DATASHEET]

Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014

7.4

ALU - Arithmetic Logic Unit

The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a

purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register

and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the

status register is updated to reflect information about the result of the operation.

ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit

arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit arithmetic. The hardware

multiplier supports signed and unsigned multiplication and fractional format.

7.4.1

Hardware Multiplier

The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different

variations of signed and unsigned integer and fractional numbers:

Multiplication of unsigned integers

Multiplication of signed integers

Multiplication of a signed integer with an unsigned integer

Multiplication of unsigned fractional numbers

Multiplication of signed fractional numbers

Multiplication of a signed fractional number with an unsigned one

A multiplication takes two CPU clock cycles.

7.5

Program Flow

After reset, the CPU starts to execute instructions from the lowest address in the flash program memory ‘0.’ The program

counter (PC) addresses the next instruction to be fetched.

Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole

address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.

During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general

data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After

reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the

I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be

accessed through the five different addressing modes supported in the AVR CPU.

7.6

Status Register

The status register (SREG) contains information about the result of the most recently executed arithmetic or logic

instruction. This information can be used for altering program flow in order to perform conditional operations. Note that

the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many

cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.

The status register is not automatically stored when entering an interrupt routine nor restored when returning from an

interrupt. This must be handled by software.

The status register is accessible in the I/O memory space.

7.7

Stack and Stack Pointer

The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing

temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit

registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and

POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing

data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded

ATXMEGA8E5 Datasheet(PDF) 9 Page - ATMEL Corporation

ATXMEGA8E5 Datasheet(HTML) 9 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL