ATXMEGA8E5_14 datasheet(45/147 Pages) ATMEL

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XMEGA E5 [DATASHEET]

Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014

24.

USART

24.1

Features

Two identical USART peripherals

Full-duplex or one-wire half-duplex operation

Asynchronous or synchronous operation

Synchronous clock rates up to 1/2 of the device clock frequency

Asynchronous clock rates up to 1/8 of the device clock frequency

Supports serial frames with:

5, 6, 7, 8, or 9 data bits

Optionally even and odd parity bits

1 or 2 stop bits

Fractional baud rate generator

Can generate desired baud rate from any system clock frequency

No need for external oscillator with certain frequencies

Built-in error detection and correction schemes

Odd or even parity generation and parity check

Data overrun and framing error detection

Noise filtering includes false start bit detection and digital low-pass filter

Separate interrupts for

Transmit complete

Transmit data register empty

Receive complete

Multiprocessor communication mode

Addressing scheme to address a specific devices on a multidevice bus

Enable unaddressed devices to automatically ignore all frames

System wake-up from Start bit

Master SPI mode

Double buffered operation

Configurable data order

Operation up to 1/2 of the peripheral clock frequency

IRCOM module for IrDA compliant pulse modulation/demodulation

One USART is connected to XMEGA Custom Logic (XCL) module:

Extend serial frame length up to 256 bit by using the peripheral counter

Modulate/demodulate data within the frame by using the glue logic outputs

24.2

Overview

The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial

communication module. The USART supports full-duplex with asynchronous and synchronous operation and single wire

half-duplex communication with asynchronous operation. The USART can be configured to operate in SPI master mode

and used for SPI communication.

Communication is frame based, and the frame format can be customized to support a wide range of standards. The

USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate

interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow

are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can

also be enabled.

ATXMEGA8E5 Datasheet(PDF) 45 Page - ATMEL Corporation

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