ATXMEGA8E5_14 datasheet(23/147 Pages) ATMEL

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XMEGA E5 [DATASHEET]

Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014

12.

Power Management and Sleep Modes

12.1

Features

Power management for adjusting power consumption and functions

Five sleep modes

Idle

Power down

Power save

Standby

Extended standby

Power reduction register to disable clock and turn off unused peripherals in active and idle modes

12.2

Overview

Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.

This enables the Atmel AVR XMEGA microcontroller to stop unused modules to save power.

All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application

code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the

device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals

and all enabled reset sources can restore the microcontroller from sleep to active mode.

In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When

this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This

reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power

management than sleep modes alone.

12.3

Sleep Modes

Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA

microcontrollers have five different sleep modes tuned to match the typical functional stages during application

execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the

device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an

enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal

program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending

when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt

service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution

starts.

The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will

reset, start up, and execute from the reset vector.

12.3.1 Idle Mode

In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but

all peripherals, including the interrupt controller, event system and EDMA controller are kept running. Any enabled

interrupt will wake the device.

12.3.2 Power-down Mode

In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of

asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the two-

wire interface address match interrupt and asynchronous port interrupts.

ATXMEGA8E5 Datasheet(PDF) 23 Page - ATMEL Corporation

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