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ATXMEGA8E5 Datasheet(PDF) 93 Page - ATMEL Corporation |
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ATXMEGA8E5 Datasheet(HTML) 93 Page - ATMEL Corporation |
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93 / 147 page  93 XMEGA E5 [DATASHEET] Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014 Notes: 1. Required only for fSCL > 100kHz. 2. Cb = Capacitance of one bus line in pF. 3. fPER = Peripheral clock frequency. tLOW Low period of SCL Clock fSCL ≤ 100kHz 4.7 µs fSCL ≤ 400kHz 1.3 fSCL ≤ 1MHz 0.5 tHIGH High period of SCL Clock fSCL ≤ 100kHz 4 µs fSCL ≤ 400kHz 0.6 fSCL ≤ 1MHz 0.26 tSU;STA Set-up time for a repeated START condition fSCL ≤ 100kHz 4.7 µs fSCL ≤ 400kHz 0.6 fSCL ≤ 1MHz 0.26 tHD;DAT Data hold time fSCL ≤ 100kHz 0 3.45 µs fSCL ≤ 400kHz 0 0.9 fSCL ≤ 1MHz 0 0.45 tSU;DAT Data setup time fSCL ≤ 100kHz 250 ns fSCL ≤ 400kHz 100 fSCL ≤ 1MHz 50 tSU;STO Setup time for STOP condition fSCL ≤ 100kHz 4 µs fSCL ≤ 400kHz 0.6 fSCL ≤ 1MHz 0.26 tBUF Bus free time between a STOP and START condition fSCL ≤ 100kHz 4.7 µs fSCL ≤ 400kHz 1.3 fSCL ≤ 1MHz 0.5 Symbol Parameter Condition Min. Typ. Max. Units |
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