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12ASX2 Datasheet(PDF) 90 Page - Infineon Technologies AG |
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12ASX2 Datasheet(HTML) 90 Page - Infineon Technologies AG |
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90 / 147 page ![]() EiceDRIVER ™ SIL 1EDI2002AS Register Description Datasheet 90 Rev. 3.1, 2015-07-30 Hardware Description CER1 2 rhs Communication Error Primary Flag This indicates if a loss of communication event 1) with the secondary chip has been detected by the primary chip. 0 B: No event has been detected. 1 B: An event has been detected. This bit is sticky. Note: This bit can not be cleared while an error condition is active (bit PSTAT2.SRDY cleared). LMI 1 rh Last Message Invalid Notification This bit indicates if the last received SPI Message was correctly processed by the device. 0 B: Previous Message was processed correctly. 1 B: Previous Message was discarded. P 0 rh Parity Bit Odd Parity Bit. 1) This bit is not set after a reset event Field Bits Type Description |
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