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UPSD3312D Datasheet(PDF) 181 Page - STMicroelectronics |
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UPSD3312D Datasheet(HTML) 181 Page - STMicroelectronics |
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181 / 272 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) UPSD33xx PSD module Doc ID 9685 Rev 7 181/272 Drive Select 08h 09h 16h 17h Write to configure port pins as either CMOS push-pull or Open Drain on some pins, while selecting high slew rate on other pins. Read to check status. Default output type is CMOS push-pull. Table 146 on page 217 Input Macrocells 0Ah 0Bh 18h Read to obtain logic state of IMCs. No WRITEs. Table 127 on page 206 Enable Out OCh 0Dh 1Ah 1Bh Read state of output enable logic on each I/O port driver. 1 = driver output is enabled, 0 = driver is off, and it is in high impedance state. No WRITEs. Table 150 on page 217 Output Macrocells AB (MCELLAB) 20h Read logic state of MCELLAB outputs (bank of eight OMCs). Write to load MCELLAB flip-flops. Table 123 on page 204 Output Macrocells BC (MCELLBC) 21h Read logic state of MCELLBC outputs (bank of eight OMCs). Write to load MCELLBC flip-flops. Table 124 on page 204 Mask Macrocells AB 22h Write to set mask for MCELLAB. Logic '1' blocks READs/WRITEs of OMC. Logic '0' will pass OMC value. Read to check status. Table 125 on page 204 Mask Macrocells BC 23h Write to set mask for MCELLBC. Logic '1' blocks READs/WRITEs of OMC. Logic '0' will pass OMC value. Read to check status. Table 126 on page 204 Main Flash Sector Protection C0h Read to determine Main Flash Sector Protection Setting (non-volatile) that was specified in PSDsoft Express. No WRITEs. Table 119 on page 193 Security Bit and Secondary Flash Sector Protection C2h Read to determine if PSD module device Security Bit is active (non- volatile) Logic 1 = device secured. Also read to determine Secondary Flash Protection Setting (non-volatile) that was specified in PSDsoft. No WRITEs. Table 120 on page 193 PMMR0 B0h Power Management register 0. WRITE and READ. Table 154 on page 225 PMMR2 B4h Power Management register 2. WRITE and READ. Table 155 on page 226 Table 116. CSIOP registers and their Offsets (in hexadecimal (continued) Register name Port A (80- pin) Port B Port C Port D Other Description Link |
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