UPSD3312D datasheet(183/272 Pages) STMICROELECTRONICS

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UPSD33xx

PSD module

Doc ID 9685 Rev 7

183/272

PSD module device are completely independent, the 8032 may read code from one array

while sending instructions to the other. It is possible, however, to suspend a sector erase

operation in one particular Flash array in order to access a different sector within that same

Flash array, then resume the erase later.

After a Flash memory array is programmed or erased it will go to “Read Array” mode, then

the 8032 can read from Flash memory just as it would read from any 8-bit ROM or SRAM

device.

27.4.2

Flash memory instruction sequences

An instruction sequence consists of a sequence of specific byte WRITE and byte READ

operations. Each byte written to either Flash memory array on the PSD module is received

by a state machine inside the Flash array and sequentially decoded to execute an

embedded algorithm. The algorithm is executed when the correct number of bytes are

properly received and the time between two consecutive bytes is shorter than the timeout

period of 80µs. Some instruction sequences are structured to include READ operations

after the initial WRITE operations.

An instruction sequence must be followed exactly. Any invalid combination of instruction

bytes or timeout between two consecutive bytes while addressing Flash memory resets the

PSD module Flash logic into Read Array mode (where Flash memory is read like a ROM

device). The Flash memories support instruction sequences summarized in Table 117 on

page 184.

●

Program a byte

●

Unlock Sequence Bypass

●

Erase memory by array or by sector

●

Suspend or resume a sector erase

●

Reset to Read Array mode

The first two bytes of an instruction sequence are 8032 bus WRITE operations to “unlock”

the Flash array, followed by writing a command byte. The bus operations consist of writing

the data AAh to address X555h during the first bus cycle and data 55h to address XAAAh

during the second bus cycle. 8032 address signals A12-A15 are “Don’t care” during the

instruction sequence during WRITE cycles. However, the appropriate sector select signal

(FSx or CSBOOTx) from the DPLD must be active during the entire instruction sequence to

complete the entire 8032 address (this includes the page number when memory paging is

used). Ignoring A12-A15 means the user has more flexibility in memory mapping. For

example, in many traditional Flash memories, instruction sequences must be written to

addresses AAAAh and 5555h, not XAAAh and X555h like supported on the PSD module.

When AAAAh and 5555h must be written to, the memory mapping options are limited.

The main Flash and secondary Flash memories each have the same instruction set shown

in Table 117 on page 184, but the sector select signals determine which memory array will

receive and execute the instructions.

UPSD3312D Datasheet(PDF) 183 Page - STMicroelectronics

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