UPSD3312D datasheet(182/272 Pages) STMICROELECTRONICS

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Doc ID 9685 Rev 7

27.4

PSD module detailed operation

Specific details are given here for the following key functional areas on the PSD module:

●

Flash memories

●

PLDs (DPLD and GPLD)

●

I/O ports

●

Power management

●

JTAG ISP and debug interface

27.4.1

Flash memory operation

The Flash memories are accessed through the 8032 Address, Data, and Control Bus

interfaces. Flash memories (and SRAM) cannot be accessed by any other bus master other

than the 8032 MCU (these are not dual-port memories).

The 8032 cannot write to Flash memory as it would an SRAM (supply address, supply data,

supply WR strobe, assume the data was correctly written to memory). Flash memory must

first be “unlocked” with a special instruction sequence of byte WRITE operations to invoke

an internal algorithm inside either Flash memory array, then a single data byte is written

(programmed) to the Flash memory array, then programming status is checked by a byte

READ operation or by checking the Ready/Busy pin (PC3). Table 117 on page 184 lists all

of the special instruction sequences to program a byte to either of the Flash memory arrays,

erase the arrays, and check for different types of status from the arrays.

This unlocking sequence is typical for many Flash memories to prevent accidental WRITEs

by errant code. However, it is possible to bypass this unlocking sequence to save time while

intentionally programming Flash memory.

IMPORTANT: The 8032 may not read and execute code from the same Flash memory array

for which it is directing an instruction sequence. Or more simply stated, the 8032 may not

read code from the same Flash array that is writing or erasing. Instead, the 8032 must

execute code from an alternate memory (like SRAM or a different Flash array) while sending

instruction sequences to a given Flash array. Since the two Flash memory arrays inside the

PMMR3

C7h

Power Management register 3. WRITE

and READ. However, Bit 1 can be

cleared only by a reset condition.

Table 156

page 226

Page

E0h

Memory Page register. WRITE and

READ.

Figure 51

page 167

VM (Virtual

memory)

E2h

Places PSD module memories into

8032 Program Address Space and/or

8032 XDATA Address Space. (VM

overrides initial non-volatile setting that

was specified in PSDsoft Express.

Reset restores initial setting)

Table 115

page 178

Table 116.

CSIOP registers and their Offsets (in hexadecimal (continued)

name

Port A

(80-

pin)

Port B

Port C

Port D

Other

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