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UPSD3312D Datasheet(PDF) 256 Page - STMicroelectronics |
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UPSD3312D Datasheet(HTML) 256 Page - STMicroelectronics |
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256 / 272 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) DC and AC parameters UPSD33xx 256/272 Doc ID 9685 Rev 7 Figure 90. Synchronous Clock mode timing – PLD Table 176. CPLD macrocell synchronous Clock mode timing (5 V PSD module) Symbol Parameter Conditions Min Max PT Aloc Turbo Off Slew rate(1) 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount. Unit fMAX Maximum frequency external feedback 1/(tS+tCO)40.0 MHz Maximum frequency internal feedback (fCNT) 1/(tS+tCO–10) 66.6 MHz Maximum frequency pipelined data 1/(tCH+tCL)83.3 MHz tS Input setup time 12 + 2 + 10 ns tH Input hold time 0 ns tCH Clock high time Clock Input 6 ns tCL Clock low time Clock Input 6 ns tCO Clock to output delay Clock Input 13 – 2 ns tARD CPLD array delay Any macrocell 11 + 2 ns tMIN Minimum clock period(2) 2. CLKIN (PD1) tCLCL = tCH + tCL.105 tCH+tCL 12 ns tCH tCL tCO tH tS CLKIN INPUT REGISTERED OUTPUT AI02860 |
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