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UPSD3312D Datasheet(PDF) 257 Page - STMicroelectronics

Part # UPSD3312D
Description  fast 8032 MCU with programmable logic
PDF  272 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UPSD3312D Datasheet(HTML) 257 Page - STMicroelectronics

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Obsolete
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UPSD33xx
DC and AC parameters
Doc ID 9685 Rev 7
257/272
Table 177.
CPLD macrocell synchronous Clock mode timing (3 V PSD module)
Figure 91.
Asynchronous RESET / Preset
Figure 92.
Asynchronous Clock mode timing (product term clock)
Symbol
Parameter
Conditions
Min
Max
PT Aloc
Turbo
Off
Slew
rate(1)
1.
Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.
Unit
fMAX
Maximum frequency
external feedback
1/(tS+tCO)23.2
MHz
Maximum frequency
internal feedback
(fCNT)
1/(tS+tCO–
10)
30.3
MHz
Maximum frequency
pipelined data
1/(tCH+tCL)40.0
MHz
tS
Input setup time
20
+ 4
+ 15
ns
tH
Input hold time
0
ns
tCH
Clock high time
Clock Input
15
ns
tCL
Clock low time
Clock Input
10
ns
tCO
Clock to output delay
Clock Input
23
– 6
ns
tARD
CPLD array delay
Any
macrocell
20
+ 4
ns
tMIN
Minimum clock
period(2)
2.
CLKIN (PD1) tCLCL = tCH + tCL.
tCH+tCL
25
ns
tARP
REGISTER
OUTPUT
tARPW
RESET/PRESET
INPUT
AI02864
tCHA
tCLA
tCOA
tHA
tSA
CLOCK
INPUT
REGISTERED
OUTPUT
AI02859



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