UPSD3312D datasheet(261/272 Pages) STMICROELECTRONICS

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UPSD33xx

DC and AC parameters

Doc ID 9685 Rev 7

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Figure 94.

Peripheral I/O READ timing

Table 183.

Port A peripheral data mode READ timing (5 V PSD module)

Table 184.

Port A peripheral data mode READ Timing (3 V PSD module)

tRLQV (PA)

tDVQV (PA)

tRHQZ (PA)

tSLQV (PA)

tAVQV (PA)

ADDRESS

DATA VALID

ALE

A /D BUS

DATA ON PORT A

CSI

AI06610

Symbol

Parameter

Conditions

Min

Max

Turbo

off

Unit

tAVQV–PA

Address valid to data valid

(1)

Any input used to select Port A Data Peripheral mode.

+ 10

tSLQV–PA

CSI valid to data valid

+ 10

tRLQV–PA

RD to data valid

(2)

Data is already stable on Port A.

tDVQV–PA

Data In to data out valid

tRHQZ–PA RD to data high-Z

Symbol

Parameter

Conditions

Min

Max

Turbo off Unit

tAVQV–PA

Address valid to data valid

(1)

Any input used to select Port A Data Peripheral mode.

+ 15

tSLQV–PA

CSI valid to data valid

+ 15

tRLQV–PA

RD to data valid

(2)

Data is already stable on Port A.

tDVQV–PA

Data In to data out valid

tRHQZ–PA RD to data high-Z

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