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UPSD3312D Datasheet(PDF) 263 Page - STMicroelectronics |
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UPSD3312D Datasheet(HTML) 263 Page - STMicroelectronics |
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263 / 272 page ![]() Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) UPSD33xx DC and AC parameters Doc ID 9685 Rev 7 263/272 Figure 96. ISC timing Table 188. ISC timing (5 V PSD module) Symbol Parameter Conditions Min Max Unit tISCCF Clock (TCK, PC1) frequency (except for PLD) (1) 1. For non-PLD Programming, Erase or in ISC By-pass mode. 20 MHz tISCCH Clock (TCK, PC1) high time (except for PLD) (1) 23 ns tISCCL Clock (TCK, PC1) low time (except for PLD) (1) 23 ns tISCCFP Clock (TCK, PC1) frequency (PLD only) (2) 2. For Program or Erase PLD only. 4MHz tISCCHP Clock (TCK, PC1) high time (PLD only) (2) 90 ns tISCCLP Clock (TCK, PC1) low time (PLD only) (2) 90 ns tISCPSU ISC Port setup time 7 ns tISCPH ISC Port hold up time 5 ns tISCPCO ISC Port clock to output 21 ns tISCPZV ISC Port high-impedance to valid output 21 ns tISCPVZ ISC Port valid output to high-impedance 21 ns ISCCH TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO t ISCCL t ISCPH t ISCPSU t ISCPVZ t ISCPZV t ISCPCO t AI02865 |
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