UPSD3312D datasheet(264/272 Pages) STMICROELECTRONICS

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DC and AC parameters

UPSD33xx

264/272

Doc ID 9685 Rev 7

Table 189.

ISC timing (3 V PSD module)

Figure 97.

MCU module AC measurement I/O waveform

AC inputs during testing are driven at VCC–0.5 V for a logic '1,' and 0.45 V for a logic '0.'

Timing measurements are made at VIH(min) for a logic '1,' and VIL(max) for a logic '0'

Figure 98.

PSD module AC float I/O waveform

For timing purposes, a Port pin is considered to be no longer floating when a 100mV change from load

voltage occurs, and begins to float when a 100mV change from the loaded VOH or VOL level occurs

IOL and IOH ≥ 20 mA

Symbol

Parameter

Conditions

Min

Max

Unit

tISCCF

Clock (TCK, PC1) frequency (except for PLD)

(1)

For non-PLD Programming, Erase or in ISC By-pass mode.

MHz

tISCCH

Clock (TCK, PC1) high time (except for PLD)

(1)

tISCCL

Clock (TCK, PC1) low time (except for PLD)

(1)

tISCCFP Clock (TCK, PC1) frequency (PLD only)

(2)

For Program or Erase PLD only.

4MHz

tISCCHP Clock (TCK, PC1) high time (PLD only)

(2)

tISCCLP Clock (TCK, PC1) low time (PLD only)

(2)

tISCPSU ISC Port setup time

tISCPH

ISC Port hold up time

tISCPCO ISC Port clock to output

tISCPZV ISC Port high-impedance to valid output

tISCPVZ ISC Port valid output to high-impedance

AI06650

VCC – 0.5V

0.45V

Test Points

0.2 VCC – 0.1V

0.2 VCC + 0.9V

AI06651

Test Reference Points

VOL + 0.1V

VOH – 0.1V

VLOAD – 0.1V

VLOAD + 0.1V

0.2 VCC – 0.1V

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