UPSD3312D datasheet(262/272 Pages) STMICROELECTRONICS

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DC and AC parameters

UPSD33xx

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Doc ID 9685 Rev 7

Figure 95.

Peripheral I/O WRITE timing

Table 185.

Port A peripheral data mode WRITE Timing (5 V PSD module)

Table 186.

Port A peripheral data mode WRITE Timing (3 V PSD module)

Table 187.

Supervisor Reset and LVD.

tDVQV (PA)

tWLQV

(PA)

tWHQZ (PA)

ADDRESS

DATA OUT

A / D BUS

PORT A

DATA OUT

ALE

AI06611

Symbol

Parameter

Conditions

Min

Max

Unit

tWLQV–PA WR to data propagation delay

tDVQV–PA

Data to Port A data propagation delay

(1)

Data stable on Port 0 pins to data on Port A.

tWHQZ–PA WR Invalid to Port A Tri-state

Symbol

Parameter

Conditions

Min

Max

Unit

tWLQV–PA WR to data propagation delay

tDVQV–PA

Data to Port A data propagation delay

(1)

Data stable on Port 0 pins to data on Port A.

tWHQZ–PA WR Invalid to Port A Tri-state

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tRST_LO_IN

Reset input duration

1(1)

25µs minimum to abort a Flash memory program or erase cycle in progress.

µs

tRST_ACTV

Generated Reset duration

fOSC = 40 MHz

10(2)

As FOSC decreases, tRST_ACTV increases. Example: tRST_ACTV = 50ms when FOSC = 8 MHz

tRST_FIL

Reset input spike filter

µs

VRST_HYS

Reset input hysteresis

VCC = 3.3 V

0.1

VRST_THRE

LVD trip threshold

VCC = 3.3 V

2.4

2.6

2.8

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