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UPSD3312D Datasheet(PDF) 253 Page - STMicroelectronics |
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UPSD3312D Datasheet(HTML) 253 Page - STMicroelectronics |
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253 / 272 page ![]() Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) UPSD33xx DC and AC parameters Doc ID 9685 Rev 7 253/272 Table 170. n, m, and x, y values Figure 88. External WRITE cycle (80-pin device only) Table 171. External WRITE cycle AC characteristics (3 V or 5 V device) # of PFQCLK in BUSCON register PSEN (code) cycle READ cycle WRITE cycle nm n m x y 3 1 2 ---- 4 2 3 2321 5 3 4 3432 6 4 5 4543 7 - - 5654 MCU A8 - A11 MCU AD0 - AD7 ALE WR PSEN A8-A11 A8-A11 tLLWL tWLWH tAVLL tLHLL tQVWH DATA OUT A0-A7 INSTR IN A0-A7 tLLAX tAVWL tWHQX tWHLH AI07877 Symbol Parameter 40 MHz oscillator(1) 1. BUSCON register is configured for 4 PFQCLK. Variable oscillator 1/tCLCL = 8 to 40 MHz Unit Min Max Min Max tLHLL ALE pulse width 17 tCLCL – 8 ns tAVLL Address Setup to ALE 13 tCLCL – 12 ns tLLAX Address hold after ALE 7.5 0.5tCLCL – 5 ns tWLWH WR pulse width(2) 2. Refer to Table 172 for “n” and “m” values. 40 xtCLCL – 10 ns tLLWL ALE to WR 7.5 0.5tCLCL – 5 ns tAVWL Address valid to WR 27.5 1.5tCLCL – 10 ns tWHLH WR high to ALE high 6.5 14.5 0.5tCLCL – 6 0.5tCLCL + 2 ns tQVWH Data setup before WR(y) 20 ytCLCL – 5 ns tWHQX Data hold after WR 6.5 14.5 0.5tCLCL – 6 0.5tCLCL + 2 ns |
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