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UPSD3312D Datasheet(PDF) 252 Page - STMicroelectronics |
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UPSD3312D Datasheet(HTML) 252 Page - STMicroelectronics |
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252 / 272 page ![]() Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) DC and AC parameters UPSD33xx 252/272 Doc ID 9685 Rev 7 Figure 87. External PSEN/READ cycle (80-pin device only) Table 169. External PSEN or READ cycle AC Characteristics (3 V or 5 V device) tAVLL tPLPH tPXIZ tAVIV PSEN MCU AD0 - AD7 MCU A8 - A11 AI07875 tLHLL ALE RD tLLPL A0-A7 tLLAX tAZPL A0-A7 tPXAV tPXIX A8-A11 INSTR IN A8-A11 Symbol Parameter 40 MHz oscillator(1) 1. BUSCON register is configured for 4 PFQCLK. Variable oscillator 1/tCLCL = 8 to 40 MHz Unit Min Max Min Max tLHLL ALE pulse width 17 tCLCL – 8 ns tAVLL Address setup to ALE 13 tCLCL – 12 ns tLLAX Address hold after ALE 7.5 0.5tCLCL – 5 ns tLLPL ALE to PSEN or RD 7.5 0.5tCLCL – 5 ns tPLPH PSEN or RD pulse width(2) 2. Refer to Table 170 for “n” and “m” values. 40 ntCLCL – 10 ns tPXIX Input instruction/data hold after PSEN or RD 22 ns tPHIZ Input instruction/data float after PSEN or RD 10.5 0.5tCLCL – 2 ns tPXAV Address hold after PSEN or RD 7.5 0.5tCLCL – 5 ns tAVIV Address to valid instruction/data in(2) 70 mtCLCL – 5 ns tAZPL Address float to PSEN or RD –2 –2 ns |
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