DRV10983ZPWPR datasheet(35/58 Pages) TI1

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Motor phase

driving voltage

Fgcycle '00'

4 pole

Fgcycle '01'

6 pole

Fgcycle '10'

8 pole

Fgcycle '11'

12 pole

DRV10983

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SLVSCP6C – JULY 2014 – REVISED MAY 2016

Product Folder Links: DRV10983

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Figure 36 shows the DRV10983 has been configured to provide FG pulses once every electrical cycle (4 pole),

twice every three electrical cycle (6 pole), once every two electrical cycles (8 pole), and once every three

electrical cycles (12 pole).

Note that when it is set to 2 FG pulses every three electrical cycles, the FG output is not 50% duty cycle. Motor

speed is able to be measured by monitoring the rising edge of the FG output.

Figure 36. FG Frequency Divider

9.4.10.2 FG Open Loop and Lock Behavior

Note that the FG output reflects the driving state of the motor. During normal closed loop behavior, the driving

state and the actual state of the motor are synchronized. During open loop acceleration, however, this may not

reflect the actual motor speed. During a locked motor condition, the FG output is driven high.

The DRV10983 provides three options for controlling the FG output during open loop as shown in Figure 37. The

selection of these options is determined by the FGOLSel[1:0] setting.

•

Option0: Open loop output FG based on driving frequency

•

Option1: Open loop no FG output (keep high)

•

Option2: FG output based on driving frequency at the first power-on startup, and no FG output (keep high) for

any subsequent restarts

DRV10983ZPWPR Datasheet(PDF) 35 Page - Texas Instruments