CP3SP33SMSSLASHNOPB datasheet(260/407 Pages) TI1

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CVSD/PCM Converter 0

CVSDIN0

CVSDOUT0

PCMOUT0

PCMIN0

CVSDIN1

CVSDOUT1

PCMOUT1

PCMIN1

ATDR1

ARDR1

ATDR0

ARDR0

DS435

AAI

CVSD/PCM Converter 1

Bluetooth RAM

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

When the CVSDOUT0 contains 5 entries or more, a DMA transfer is requested. If CVSDOUT0 is assigned

to device A and the DIR bit in the DMA channel control register is clear, the DMA controller reads data

from the CVSDOUT0 (device A) and writes the data into the Bluetooth RAM (device B).

The CVSD/PCM module introduces an effective compression ratio of 2 to 1, so an audio sample rate of 8

ksps results in DMA transfers on both the CVSDIN and CVSDOUT DMA channels at a rate of 4k transfers

per second.

26.9.2 Dual CVSD Channels to Bluetooth HCI

This usage model is illustrated in Figure 26-4 and consists of the following operations.

•

Two bidirectional CVSD channels through the Bluetooth LLC.

•

CVSD/PCM conversion done on-chip.

•

PCM audio data is transferred between the CVSD/PCM modules and the system RAM by DMA.

•

CVSD audio data is transferred between the CVSD/PCM modules and the Bluetooth RAM by DMA.

•

CVSD/PCM modules operate in free-running mode, in which the sample throughput is determined by

the frequency of Auxiliary Clocks 2 and 3.

Figure 26-4. Dual CVSD Channels to Bluetooth HCI

26.9.2.1 PCM Transmit Data Path

The CVSD/PCM modules have DMA channels assigned to their PCMINn registers. DMA data transfers

from system RAM to the CVSD/PCM modules use indirect transfers, in which each transfer is performed

with two adjacent bus cycles (read/write). The operation of the PCMIN0 DMA channel of CVSD/PCM

module 0 is described below. The PCMIN1 DMA channel operates in a similar way.

The CVSD/PCM module requests a DMA transfer each time a PCM sample has been processed. If

PCMIN0 is assigned to device A and the DIR bit in the DMA channel control register is set, the DMA

controller reads data from system RAM (device B) and writes the data into the PCMIN0 register (device

A). The DMA controller must be configured so that automatic update of the device A (PCMIN0) address is

disabled. The address of device B (system RAM) must be configured to automatically increment or

decrement by 2 after each DMA transfer.

CVSD/PCM module 0 requires 250 clock cycles of Auxiliary Clock 2 (Auxiliary Clock 3 for CVSD/PCM

module 1) to encode a single PCM sample. The effective compression ratio of 2 to 1 from PCM to CVSD

means that a new 16-bit CVSD-encoded data word is produced every 500 cycles. Every 250 cycles, a

DMA operation is requested to transfer a PCM sample for the next cycle of the encoder. Similarly, every

500 cycles, a DMA operation is requested to transfer a CVSD data word from the CVSD/PCM module to

memory. The frequency of the Auxiliary Clock determines the time interval between successive DMA

requests.

For example, if the Auxiliary Clock is 2 MHz, the CVSD/PCM module will request a DMA transfer on the

PCMINn channel at a rate of 8 ksps. If the Auxiliary Clock is 12 MHz, the DMA transfer rate will be 48

ksps.

260

Dual CVSD/PCM Conversion Modules

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