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CP3SP33SMS/NOPB Datasheet(PDF) 272 Page - Texas Instruments |
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CP3SP33SMS/NOPB Datasheet(HTML) 272 Page - Texas Instruments |
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272 / 407 page  3 Start Bit 9-Bit Data 1S 3a Start Bit 9-Bit Data 2S DS065 CP3SP33 SNOSCW5 – MAY 2013 www.ti.com The format shown in Figure 27-6 consists of one start bit, nine data bits, and one or two stop bits. This format also supports the UART attention feature. When operating in this format, all eight bits of UnTBUF and UnRBUF are used for data. The ninth data bit is transmitted and received using two bits in the control registers, called UXB9 and URB9. Parity is not generated or verified in this mode. Figure 27-6. . 9-bit Data Frame Options 27.2.6 Baud Rate Generator The Baud Rate Generator creates the basic baud clock from the PCLK Clock. The PCLK Clock is passed through a two-stage divider chain consisting of a 5-bit baud rate prescaler (UnPSC) and an 11-bit baud rate divisor (UnDIV). The relationship between the 5-bit prescaler select (UnPSC) setting and the prescaler factors is shown in Table 27-1. Table 27-1. Prescaler Factors PRESCALER PRESCALER FACTOR PRESCALER SELECT PRESCALER FACTOR SELECT 00000 No clock 10000 8.5 00001 1 10001 9 00010 1.5 10010 9.5 00011 2 10011 10 00100 2.5 10100 10.5 00101 3 10101 11 00110 3.5 10110 11.5 00111 4 10111 12 01000 4.5 11000 12.5 01001 5 11001 13 01010 5.5 11010 13.5 01011 6 11011 14 01100 6.5 11100 14.5 01101 7 11101 15 01110 7.5 11110 15.5 01111 8 11111 16 A prescaler factor of zero corresponds to “no clock.” The “no clock” condition is the UART power down mode, in which the UART clock is turned off to reduce power consumption. Software must select the “no clock” condition before entering a new baud rate. Otherwise, it could cause incorrect data to be received or transmitted. The UnPSR register must contain a value other than zero when an external clock is used at CKX. 272 Dual/Quad UART Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :CP3SP33 |
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