CP3SP33SMSSLASHNOPB datasheet(276/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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27.3.1 UART Interrupt Control Register (UnICTRL)

The UnICTRL registers are 8-bit, read/write registers that contain the receive and transmit interrupt status

bits (read-only bits) and the interrupt enable bits (read/write bits). The register is initialized to 01h at reset.

UEEI

UERI

UETI

UEFCI

UCTS

UDCTS

URBF

UTBE

The Transmit Buffer Empty bit is set by hard- ware when the UART transfers data from the

UnTBUF register to the transmit shift register for transmission. It is automatically cleared by

the hardware on the next write to the UnTBUF register.

0 – Transmit buffer is loaded.

1 – Transmit buffer is empty.

URBF

The Receive Buffer Full bit is set by hardware when the UART has received a complete data

frame and has transferred the data from the receive shift register to the UnRBUF register. It is

automatically cleared by the hardware when the UnRBUF register is read.

0 – Receive buffer is empty.

1 – Receive buffer is loaded.

UDCTS

The Delta Clear To Send bit indicates whether the CTSn input has changed state since the

CPU last read this register. This bit is only used with UART0, UART1, and UART2.

0 – No change since last read.

1 – State has changed since last read.

UCTS

UCTS The Clear To Send bit indicates the state on the CTS input. This bit is only used with

UART0, UART1, and UART2.

0 – CTSn input is high.

1 – CTSn input is low.

UEFCI

The Enable Flow Control Interrupt bit controls whether a flow control interrupt is asserted

when the UDCTS bit changes from clear to set. This bit is only used with UART0, UART1, and

UART2.

0 – Flow control interrupt disabled.

1 – Flow control interrupt enabled.

UETI

The Enable Transmitter Interrupt bit, when set, enables generation of an interrupt when the

hardware sets the UTBE bit.

0 – Transmit buffer empty interrupt disabled.

1 – Transmit buffer empty interrupt enabled.

UERI

The Enable Receiver Interrupt bit, when set, enables generation of an interrupt when the

hardware sets the URBF bit.

0 – Receive buffer full interrupt disabled.

1 – Receive buffer full interrupt enabled.

UEEI

The Enable Receive Error Interrupt bit, when set, enables generation of an interrupt when the

hardware sets the UERR bit in the Un-STAT register.

0 – Receive error interrupt disabled.

1 – Receive error interrupt enabled.

27.3.2 UART Status Register (UnSTAT)

The UnSTAT registers are 8-bit, read-only registers that contain the receive and transmit status bits.

These registers are cleared at reset. Any attempt by software to write to these registers is ignored. The

Reserved

UXMIP

URB9

UBKD

UERR

UDOE

UFE

UPE

276

Dual/Quad UART

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