| Electronic Components Datasheet Search |
|
CP3SP33SMS/NOPB Datasheet(PDF) 282 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
CP3SP33SMS/NOPB Datasheet(HTML) 282 Page - Texas Instruments |
|
282 / 407 page ![]() CLK BR (2 N P) u u CP3SP33 SNOSCW5 – MAY 2013 www.ti.com 27.4.2 Synchronous Mode Synchronous mode is only available for the UART0 module. When synchronous mode is selected and the UCKS bit is set, the UART operates from a clock received on the CKX pin. When the UCKS bit is clear, the UART uses the clock from the internal baud rate generator which is also driven on the CKX pin. When the internal baud rate generator is used, the equation for calculating the baud rate is: (11) where BR is the baud rate, CLK is the PCLK Clock, N is the value of the baud rate divisor + 1, and P is the prescaler divide factor selected by the value in the UnPSR register. Oversampling is not used in synchronous mode. Use the same procedure to determine the values of N and P as in the asynchronous mode. In this case, however, only integer prescaler values are allowed. 282 Dual/Quad UART Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :CP3SP33 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |