CP3SP33SMSSLASHNOPB datasheet(298/407 Pages) TI1

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SDA

1 - 7

ACK

Data

Address

SCL

Stop

Condition

Start

Condition

1 - 7

R/W

Data

ACK

AC K

DS079

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

The address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends

on the bit sent after the address (the eighth bit). A low-to-high transition during a SCL high period

indicates the Stop Condition, and ends the transaction (Figure 29-5).

Figure 29-5. A Complete ACCESS.bus Data Transaction

When the address is sent, each device in the system compares this address with its own. If there is a

match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state

of the R/W bit (1 = read, 0 = write), the device acts as a transmitter or a receiver.

The ACCESS.bus protocol allows sending a general call address to all slaves connected to the bus. The

first byte sent specifies the general call address (00h) and the second byte specifies the meaning of the

general call (for example, “Write slave address by software only”). Those slaves that require the data

acknowledge the call and become slave receivers; the other slaves ignore the call.

29.1.1.4 Arbitration on the Bus

Arbitration is required when multiple master devices attempt to gain control of the bus simultaneously.

Control of the bus is initially determined according to address bits and clock cycle. If the masters are trying

to address the same bus device, data comparisons determine the outcome of this arbitration. In master

mode, the device immediately aborts a transaction if the value sampled on the SDA lines differs from the

value driven by the device. (Exceptions to this rule are SDA while receiving data; in these cases the lines

may be driven low by the slave without causing an abort.)

The SCL signal is monitored for clock synchronization and allows the slave to stall the bus. The actual

clock period will be the one set by the master with the longest clock period or by the slave stall period.

The clock high period is determined by the master with the shortest clock high period.

When an abort occurs during the address transmission, the master that identifies the conflict should give

up the bus, switch to slave mode, and continue to sample SDA to see if it is being addressed by the

winning master on the ACCESS.bus.

29.2 ACB Functional Description

The ACB modules provides the physical layer for ACCESS.bus-compliant serial interfaces. The modules

are configurable as either master or slave devices. As slaves, the ACB modules may issue a request to

become the bus master.

29.2.1 Master Mode

An ACCESS.bus transaction starts with a master device requesting bus mastership. It sends a Start

Condition, followed by the address of the device it wants to access. If this transaction is successfully

completed, software can assume that the device has become the bus master.

For a device to become the bus master, software should perform the following steps:

1. Set the ACBnCTL1.START bit, and configure the ACBnCTL1.INTEN bit to the desired operation mode

(Polling or Interrupt). This causes the ACB to issue a Start Condition on the ACCESS.bus, as soon as

the ACCESS.bus is free (ACBnCST.BB=0). It then stalls the bus by holding SCLn low.

2. If a bus conflict is detected, (i.e., some other device pulls down the SCLn signal before this device

298

Dual ACCESS.bus Interfaces

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